AI security & verification programme

AI Verification


Building verification mechanisms for high-stakes coordination over AI development and deployment.

No single lab, evaluator, or government can make frontier AI safe on its own. As capabilities grow, safety increasingly depends on coordination, and coordination depends on trust. Our engineering team works on the technical mechanisms that underlie high-stakes coordination.

Our goal is to make it inevitable that verification mechanisms are built. We don’t have to be the ones who develop the final systems, but we do need to make sure someone — possibly ourselves — does the work. As such, we work in two ways.

  • Proactive verification tech R&D. We are developing proofs of concept of foundational verification primitives, and running full verification system prototypes.
  • Government and AI lab collaborations. Verification ultimately interfaces with governments and AI developers; we spend time speaking with and supporting any stakeholders interested in advancing verification.
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Verification Is a Ladder

Verification is a process, not a one-shot solution. A ladder of technical mechanisms can build trust towards high-stakes coordination over AI — and nuclear verification history shows how the early rungs get climbed.

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Technical notes

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Understanding Data Center Power Delivery

We mapped the power delivery systems of AI data centers. Our diagram explores the data available at each stage, measurement techniques and signals of interest for AI security.

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Network Taps — A First Test

A quick test installation of a 10G network tap for AI verification — passive vs active taps, fibre types, and what scales to production speeds.

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The Tray as a Bandwidth Boundary

We used a DPU as a tray-level bandwidth limiter — an extra layer of security for protecting model weights, achieving near line-rate encryption with hardware-offloaded IPsec.

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Side Channel Cloud

Free security and verification research infrastructure.

  • Power side channels
  • Network TAPs
  • Software-defined radios
  • Bare-metal access
  • DPUs · FPGAs · SmartNICs
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